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At the upcoming 2025 VLSI Symposium, Intel will unveil key technical details of its next-generation Intel 18A process node (1.8nm), emphasizing significant improvements over the Intel 3 (7nm) technology in terms of power, performance, and area (PPA). These advancements are expected to drive meaningful benefits across both client computing and data center platforms.

According to Intel, when comparing identical modules built on the Intel 3 and Intel 18A nodes under the same voltage (1.1V) and design complexity, the 18A process delivers a 25% performance uplift. At the same voltage and frequency, it also reduces power consumption by 36%. At a reduced voltage of 0.75V, Intel 18A shows an 18% performance increase and a 38% reduction in power usage. Furthermore, area scaling reaches a 0.72x reduction compared to Intel 3, showcasing the node's superior layout efficiency.

Intel 18A marks the company's first node to incorporate Gate-All-Around (GAA) RibbonFET transistors along with PowerVia backside power delivery network (BSPDN). These innovations collectively provide considerable gains in PPA metrics.

A side-by-side comparison of standard cell layouts reveals substantial physical scaling. The high-performance library sees cell height reduced from 240CH to 180CH, while the high-density library drops from 210CH to 160CH—representing a vertical shrink of approximately 25%. This tighter cell architecture enhances transistor density, directly contributing to improved area efficiency.

The use of PowerVia BSPDN frees up routing resources on the front side of the chip by relocating power lines to the backside, enabling more efficient signal routing and tighter layout integration. Enhancements in gate, source/drain, and contact structures further boost cell uniformity and integration density. Altogether, these improvements allow Intel 18A to achieve superior performance-per-area and energy efficiency, paving the way for more advanced and compact chip designs.

Looking ahead, Intel is expected to begin volume production of compute dies based on Intel 18A for client PCs under the “Panther Lake” platform in late 2025. The first chips for Clearwater Forest data center systems are slated for early 2026. In addition, Intel anticipates completing the initial tape-outs for third-party chip designs using the Intel 18A process by mid-2025.

The interest in third-party development on Intel 18A is already apparent. Alongside a general technical paper on Intel 18A, the company plans to present a joint paper at the symposium describing a PAM-4 transmitter built with the 18A node and BSPDN. This collaboration involves engineers from Intel, Alphawave Semi, Apple, and NVIDIA. While this does not confirm Apple or NVIDIA's commercial adoption of Intel 18A, it strongly indicates their engagement and technical interest in the platform.

Meanwhile, TSMC has stated that nearly all of its partners are planning to adopt its N2 (2nm) process, suggesting a broader ecosystem alignment with that node. Nonetheless, for Intel, demonstrating its ability to deliver a competitive and manufacturable node like 18A is essential for the future of its foundry ambitions. Intel 18A is positioned to play a pivotal role in the company's roadmap as it aims to reestablish leadership in semiconductor process technology.