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According to Biwin Storage’s announcement on September 22, the company and its controlling subsidiary, Guangdong Xincheng Hanqi Semiconductor Technology Co., Ltd., plan to sign a project cooperation agreement with the Management Committee of Dongguan Songshan Lake High-Tech Industrial Development Zone. The project will involve the construction of Phase III of a wafer-level advanced packaging and testing manufacturing facility, with a total planned investment of approximately RMB 4.5 billion, including RMB 4 billion in fixed-asset investment.

According to the announcement, the Phase III project will be located in Dongguan’s Ecological Park and will be developed through expansion and additional investment within the company’s existing industrial land, without requiring new land. The project will primarily focus on expanding wafer-level advanced packaging and testing capacity, including equipment investment and factory renovation. Fixed-asset investment is scheduled to be completed by December 31, 2029. Funding will come from Guangdong Xincheng Hanqi’s own funds and self-raised capital, including third-party capital contributions and bank loans, with no proceeds from fundraising involved.

Biwin Storage’s Phase I and Phase II wafer-level advanced packaging and testing manufacturing projects have a combined planned investment of RMB 3.09 billion and have been completed, providing approximately 3,000 2.5D wafer-level packaging units per month. Phase I has completed factory construction, equipment installation, and commissioning. Equipment for Phase II is being installed and commissioned in stages, and the project is currently undergoing customer sampling, process validation, and small-batch trial production. It has not yet generated revenue from full-scale mass production.

From a technology perspective, Guangdong Xincheng Hanqi has established advanced packaging capabilities covering multiple technologies, including 2.5D, redistribution layer (RDL), Fan-in, and Fan-out packaging. Biwin Storage said Phase III will further expand its wafer-level advanced packaging and testing capabilities based on the existing projects. It will also support the commercialization and large-scale production of multi-chip system-in-package integration and compute-memory co-packaging technologies.